1. Technical Field
The embodiments described herein relate to a delay locked loop (DLL) circuit and a method of controlling the same, and more particularly, to a DLL circuit that generates an internal clock signal whose phase is more advanced than a phase of an external clock signal and a method of controlling the same.
2. Related Art
In general, a DLL circuit is used to provide an internal clock signal whose phase is more advanced than a phase of a reference clock signal obtained by converting an external clock signal by a predetermined time. The DLL circuit is also used to resolve the following problem. If an internal clock signal used in a semiconductor integrated circuit is delayed by a clock buffer and a transmission line, a phase difference is generated between the internal clock signal and an external clock signal, which results in an increase in the output data access time. As a result, in order to increase an effective data output period, a conventional DLL circuit performs a control operation such that a phase of the internal clock signal is more advanced than a phase of the external clock signal by a predetermined time.
A duty ratio of an output clock signal from a DLL circuit should be maintained at a predetermined ratio (for example, 50:50) in order to prevent the operational efficiency of a DLL circuit from deteriorating. However, the duty ratio of the output clock signal from a conventional DLL circuit may easily vary due to jitters outside the DLL circuit and irregular delay values of delay elements inside the DLL circuit. In order to prevent the duty ratio from varying, a conventional DLL circuit includes a duty cycle correction device to maintain a duty ratio of an output clock signal at a predetermined ratio.
However, the duty cycle correction apparatus that is included in a conventional DLL circuit occupies a large area and has a long operation time. Further, the operational characteristic of a conventional DLL circuit often deteriorate when operating at low power. Due to the high-speed operation, high integration, and low power consumption of today's semiconductor integrated circuits, it necessary to provide such circuits with a clock signal having an accurate duty ratio, something conventional DLL circuits cannot always do.